For use in computer systems, for example, it is known, in order to form a memory module, to arrange a plurality of memory components, for instance, in the form of DRAMs (Dynamic Random Access Memories), on a common carrier substrate. Memory modules of this type are known, in particular, as DIMMs (Registered or Buffered Dual Inline Memory Modules). The latter are typically fit with 16 or 18 memory chips, which are clock-controlled when in the form of SDRAMs or DDR DRAMs.
Integrated memories, such as DRAMs, are operated in data processing systems and in this case are driven, for example, by a microprocessor or microcontroller. Above a certain size of the memory, for example, in the case of a memory size in excess of 1 Mbit, available DRAM memories generally use a multiplex address scheme. The latter primarily serves the purpose of reducing the number of address terminals of a memory and thus the costs for the individual components in the data processing system and the power consumption of the corresponding address bus systems.
A multiplex address scheme of this type has the advantage that it matches the functionality of a DRAM memory very well. For a memory access, firstly addressed rows in the form of selected word lines and then addressed columns in the form of selected bit lines are generally activated. In the case of this address scheme, firstly row addresses and, temporally thereafter, corresponding column addresses are thus transmitted. A selection is thus made as to the memory cells from which data are read or the memory cells to which data are written. Together with address generation, a microcontroller likewise sends a plurality of individual commands, in particular, in the form of an activation signal, a read command or write command and, to conclude the memory access, a precharge command.
In order that a processor interface of a microprocessor and a DRAM interface can communicate with one another in a data processing system, for instance, a computer system, it is generally necessary to implement a memory controller (DRAM controller) in the computer system in order to convert the DRAM-specific memory access from the commands of the microprocessor. In this case, the memory controller is responsible, in particular, for mapping a logical processor address to the DRAM memory addressed and for generating the row addresses and column addresses for accessing the memory. For the purpose of realizing this functionality, registers and switching mechanisms (automatic state machines), which are suitable for this purpose, must be provided in the memory controller in order to realize this temporal multiplex address scheme. The provision of registers and switching mechanisms of this type increases the design complexity of a memory controller.